From commonly assigned patent application No. EP-A-1 324 382, which is incorporated by reference, a process is known for the manufacturing of SOI wafers by annealing and oxidation of buried channels. Said process is described briefly with reference to FIGS. 1-5.
In an initial step (FIG. 1), deep trenches 3 are formed in a silicon wafer 1 comprising a substrate 2, by means of an anisotropic etching through an appropriately shaped resist mask 4. In particular, the deep trenches 3 have a substantially rectilinear shape, extend parallel to one another, and are separated by silicon walls 5.
Next (FIG. 2), the resist mask 4 is removed and, via an epitaxial growth, a surface layer 6 of silicon is formed, closing at the top the deep trenches 3 to form a plurality of buried channels 7. Before the deep trenches 3 are closed at the top, a growth of silicon also occurs within them, causing a reduction in their dimensions. At the end of the epitaxial growth, the buried channels 7 consequently have an oval cross section elongated in a direction perpendicular to the surface of the wafer 1.
Then (FIG. 3), a thermal annealing is performed, which causes a migration of part of the silicon atoms of the walls 5 surrounding the buried channels 7, which move to a lower energy state. At the end of the annealing step, the buried channels 7 assume an approximately circular cross section, and the walls 5 thin out.
Next (FIG. 4), the wafer 1 is etched from the front to form a connection trench 8, having a depth and a size such as to reach all the buried channels 7. In particular, the connection trench 8 extends along a closed line delimiting an active area 9 of the surface layer 6, wherein integrated components are subsequently formed (active area of the SOI wafer). Oxygen is then supplied through the connection trench 8 during a step of thermal oxidation so as to oxidize completely the walls 5 and the portions of silicon that surround the buried channels 7, and partially the internal walls of the connection trench 8 and the buried channels 7. An insulating region 10 is thus formed, which electrically separates the active area 9 from the substrate 2 and forms the buried-oxide layer of the SOI wafer (FIG. 5). Finally, a layer of TEOS (TetraEthylOrthoSilicate) oxide can be deposited on the wafer 1 so as to fill the connection trench 8 and the buried channels 7 and form, with the insulating region 10, a single insulating structure.
The above process involves considerably lower costs as compared to traditional type processes. Furthermore, it has the advantages of enabling almost complete elimination of low-frequency parasitics, which are responsible for approximately 90% of the active silicon layer failures, and substrate gettering, thus ensuring a good quality of gate oxides (for CMOS or DMOS devices).
However, said process may also have some drawbacks.
In the first place, SOI wafers thus formed may have a higher thermal resistance (Rth) than SOI wafers formed with traditional type manufacturing processes: for example, it may be shown that the DC thermal resistance of a power LDMOS integrated in the SOI wafer active area undergoes an increase of approximately 25% as compared to the thermal resistance of a power LDMOS integrated in a traditional type SOI wafer. This is principally due to the presence, within the buried-oxide layer, of empty areas or voids set at regular intervals apart and not filled with dielectric material. In particular, empty areas can also remain even if filling with TEOS has been performed.
The buried-oxide layer moreover has undulations (FIG. 5) at the interface with the silicon, which may further reduce the quality of the SOI wafer as far as electrical characteristics are concerned.
Furthermore, the thickness of the buried-oxide layer formed through said process may be excessively high for normal (i.e., non-power) applications.
To reduce some of said problems, and in particular to eliminate the empty areas within the buried-oxide layer, it has been proposed to prolong the step of oxidation (pronounced oxidation) and to use shallower trenches. Furthermore, it has been proposed to act on the ratio width/depth of the trenches to reduce both the thickness of the buried-oxide layer and the undulations at the interface with the silicon. Said solutions have, however, proven not altogether satisfactory both because they may not provide a total reduction of the empty areas within the buried-oxide layer, and because the pronounced oxidation may cause stress in the adjacent silicon regions, which can lead to crystallographic defects (in the form of dislocations).